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64mx72bits pc100 sdram unbuffered dimm based on 32mx8 sdram with lv ttl, 4 banks & 8k refresh this document is a general product descripti on and is subject to change without notice. hynix semiconductor inc. does not assum e any responsibility for use of circuits described. no patent licenses are implied. rev. 0.2/jul. 02 1 hym72v64756b(l)t8 series description the hym72v64756b(l)t8 h-series are high speed 3.3-volt synchronous dynamic ram modules composed of eighteen 32mx8 bit synchronous drams in 54-pin tsopii and 8-pin tssop 2k bit eeprom on a 168-pin glass-epoxy printed circuit board. one 0.33mf and one 0.1mf decoupling capa citors per each sdram are mounted on the module. the hym72v64756b(l)t8 h-series are gold plated socket ty pe dual in-line memory mo dules suitable for easy inter- change and addition of 512m bytes memory. all addresses, data and control inputs are latched on the rising edge of the master clock input. the data paths are internally pipelined to achieve very high bandwidths. features ? 1.15 (29.21mm) pcb height ? 168-pin unbuffered di mm with double sided ? one 0.33 f and one 0.1 f decoupling capacitors adopted ? ecc support ? serial presence dete ct with serial eeprom ? meets all the other jedec specifications ? single 3.3v 0.3v power supply ? all device pins are lvttl compatible ? 8192 refresh cycles / 64ms ? fully synchronous ; all inputs referenced to posi- tive edge of system clock ? dual or quad internal ban ks with single pulsed /ras ? auto precharge/precharge all banks by a 10 flag ? possible to assert random column address every clock cycle ? interleaved auto refresh mode ? programmable burst lengths and sequences - 1,2,4,8,full page for sequential type - 1,2,4,8 for interleave type ? programmable /cas latency ; 2,3 clocks ? support clock suspend/power down mode by cke0, cke1 ? data mask function by dqm ? mode register set programming ? burst termination command ? self refresh provides minimum power, full internal refresh control ordering information part no. clock frequency internal bank ref. power sdram package plating hym72v64756bt8-p 100mhz 4 banks 8k normal tsop-ii gold hym72v64756bt8-s 100mhz HYM72V64756BLT8-P 100mhz low power hym72v64756blt8-s 100mhz
pc100 sdram unbuffered dimm rev. 0.2/jul. 02 2 hym72v64756b(l)t8 series pin description pin pin name description ck0~ck3 clock inputs the system clock input. al l other inputs are registered to the sdram on the rising edge of clk cke0,cke1 clock enable controls internal clock signal and wh en deactivated, the sdram will be one of the states among power down, suspend or self refresh /s0~/s3 chip select enables or disabl es all inputs except ck, cke and dqm ba0, ba1 sdram bank address selects bank to be activated during /ras activity selects bank to be read/written during /cas activity a0 ~ a12 address row address : ra0 ~ ra12, column address : ca0 ~ ca9 auto-precharge flag : a10 /ras, /cas, /we row address strobe, column address strobe, write enable /ras, /cas and /we define the operation refer function truth table for details dqm0~dqm7 data input/output mask controls output buffers in read mode and masks input data in write mode dq0 ~ dq63 data input/output multiplexed data input / output pin vcc power supply (3.3v) power supply fo r internal circuits and input buffers v ss ground ground scl spd clock input serial presence detect clock input sda spd data input/output serial presence detect data input/output cb0~cb7 check bit input/output check bits for ecc sa0~2 spd address input serial presence detect address input wp write protect for spd write protect for serial presence detect on dimm nc no connection no connection
pc100 sdram unbuffered dimm rev. 0.2/jul. 02 3 hym72v64756b(l)t8 series pin assignments front side back side front side back side pin no. name pin no. name pin no. name pin no. name 1 vss 85 vss 41 vcc 125 *ck1 2 dq0 86 dq32 42 ck0 126 a12 3 dq1 87 dq33 43 vss 127 vss 4 dq2 88 dq34 44 nc 128 cke0 5 dq3 89 dq35 45 /s2 129 /s3 6 vcc 90 vcc 46 dqm2 130 dqm6 7 dq4 91 dq36 47 dqm3 131 dqm7 8 dq5 92 dq37 48 nc 132 nc 9 dq6 93 dq38 49 vcc 133 vcc 10 dq7 94 dq39 50 nc 134 nc achitecture key 51 nc 135 nc 52 cb2 136 cb6 11 dq8 95 dq40 53 cb3 137 cb7 12 vss 96 vss 54 vss 138 vss 13 dq9 97 dq41 55 dq16 139 dq48 14 dq10 98 dq42 56 dq17 140 dq49 15 dq11 99 dq43 57 dq18 141 dq50 16 dq12 100 dq44 58 dq19 142 dq51 17 dq13 101 dq45 59 vcc 143 vcc 18 vcc 102 vcc 60 dq20 144 dq52 19 dq14 103 dq46 61 nc 145 nc 20 dq15 104 dq47 62 nc 146 nc 21 cb0 105 cb4 63 nc 147 nc 22 cb1 106 cb5 64 vss 148 vss 23 vss 107 vss 65 dq21 149 dq53 24 nc 108 nc 66 dq22 150 dq54 25 nc 109 nc 67 dq23 151 dq55 26 vcc 110 vcc 68 vss 152 vss 27 /we 111 /cas 69 dq24 153 dq56 28 dqm0 112 dqm4 70 dq25 154 dq57 29 dqm1 113 dqm5 71 dq26 155 dq58 30 /s0 114 /s1 72 dq27 156 dq59 31 nc 115 /ras 73 vcc 157 vcc 32 vss 116 vss 74 dq28 158 dq60 33 a0 117 a1 75 dq29 159 dq61 34 a2 118 a3 76 dq30 160 dq62 35 a4 119 a5 77 dq31 161 dq63 36 a6 120 a7 78 vss 162 vss 37 a8 121 a9 79 ck2 163 *ck3 38 a10/ap 122 ba0 80 nc 164 nc 39 ba1 123 a11 81 wp 165 sa0 40 vcc 124 vcc 82 sda 166 sa1 voltage key 83 scl 167 sa2 84 vcc 168 vcc
pc100 sdram unbuffered dimm rev. 0.2/jul. 02 4 hym72v64756b(l)t8 series block diagram note : 1. the serial resistor values of dqs are 10ohms
pc100 sdram unbuffered dimm rev. 0.2/jul. 02 5 hym72v64756b(l)t8 series serial presence detect byte number function description function value note -p -s -p -s byte0 # of bytes written into serial memory at module manufacturer 128 bytes 80h byte1 total # of bytes of spd memory device 256 bytes 08h byte2 fundamental memory type sdram 04h byte3 # of row addresses on this assembly 13 0dh 1 byte4 # of column addresses on this assembly 10 0ah byte5 # of module banks on this assembly 2 bank 02h byte6 data width of this assembly 72 bits 48h byte7 data width of this assembly (continued) - 00h byte8 voltage interf ace standard of this assembly lvttl 01h byte9 sdram cycle time @/cas latency=3 10ns 10ns a0h a0h byte10 access time from cl ock @/cas latency=3 6ns 6ns 60h 60h byte11 dimm configuration type ecc 02h byte12 refresh rate/type 7.8125us / self refresh supported 82h byte13 primary s dram width x8 08h byte14 error checking sdram width x8 08h byte15 minimum clock delay back to back random column address tccd = 1 clk 01h byte16 burst lenth supporte d 1,2,4,8,full page 8fh 2 byte17 # of banks on each sdram device 4 banks 04h byte18 sdram device attributes, /cas lataency /cas latency=2,3 /cas latency=3 06h 04h byte19 sdram device attribut es, /cs lataency /cs latency=0 01h byte20 sdram device attribut es, /we lataency /we latency=0 01h byte21 sdram module attributes ne ither buffered nor registered 00h byte22 sdram device attributes, general +/- 10% voltage tolerence, burst read single bit write, precharge all, auto precharge, early ras precharge 0eh byte23 sdram cycle time @/cas latency=2 10ns 12ns a0h c0h byte24 access time from cl ock @/cas latency=2 6ns 6ns 60h 60h byte25 sdram cycle time @/cas latency=1 - - 00h 00h byte26 access time from clock @/cas latency=1 - - 00h 00h byte27 minimum row precharge time (trp) 20ns 20ns 14h 14h byte28 minimum row active to row active delay (trrd) 20ns 20ns 14h 14h byte29 minimum /ras to /cas delay (trcd) 20ns 20ns 14h 14h byte30 minimum /ras puls e width (tras) 50ns 50ns 32h 32h byte31 module bank density 256mb 40h byte32 command and address signal input setup time 2ns 2ns 20h 20h byte33 command and address signal input hold time 1ns 1ns 10h 10h byte34 data signal input setup time 2ns 2ns 20h 20h byte35 data signal input hold time 1ns 1ns 10h 10h byte36 ~61 superset information (may be used in future) - 00h byte62 spd revision intel spd 1.2b 12h 3, 8 byte63 checksum for byte 0~62 - 4ch 6ah byte64 manufacturer jedec id code hynix jeded id adh byte65 ~71 ....manufacturer jedec id code unused ffh byte72 manufacturing location hynix (korea area) hsa (united states area) hse (europe area) hsj (japan area) hss(singapore) asia area 0*h 1*h 2*h 3*h 4*h 5*h 10
pc100 sdram unbuffered dimm rev. 0.2/jul. 02 6 hym72v64756b(l)t8 series byte number function description function value note -p -s -p -s byte73 manufacturer?s part number (component) 7 (sdram) 37h 4, 5 byte74 manufacturer?s part number (256mb based) 2 32h 4, 5 byte75 manufacturer?s part number (voltage interface) v (3.3v, lvttl) 56h 4, 5 byte76 manufacturer?s part number (memory width) 6 36h 4, 5 byte77 ....manufacturer?s part number (memory width) 4 34h 4, 5 byte78 manufacturer?s part number (data width) 7 37h 4, 5 byte79 ....manufacturer?s part number (data width) 5 35h 4, 5 byte80 manufacturer?s part number (refresh, sdram bank) 6 (8k refresh, 4banks) 36h 4, 5 byte81 manufacturer?s part number(manufacturing site) b 42h 4, 5 byte82 manufacturer?s part number (package type) t 54h 4, 5 byte83 manufacturer?s part number (component configuration) 8 (x8 based) 38h 4, 5 byte84 manufacturer?s part number (hyphent) - (hyphen) 2dh 4, 5 byte85 manufacturer?s part number (min. cycle time) p s 50h 53h 4, 5 byte86 ~90 manufacturer?s part number blanks 20h 4, 5 byte91 revision code (for component) process code - 4, 6 byte92 ....revision code (for pcb) process code - 4, 6 byte93 manufacturing date year - 3, 6 byte94 ....manufacturing date work week - 3, 6 byte95 ~98 assembly serial number serial number - 6 byte99 ~125 manufacturer specific data (may be used in future) none 00h byte126 system frequency support 100mhz 64h 7, 8 byte127 intel specification details for 100mhz support refer to note7 ffh fdh 7, 8 byte128 ~256 unused storage locations - 00h continued note : 1. the bank address is excluded 2. 1, 2, 4, 8 for interleave burst type 3. bcd adopted 4. ascii adopted 5. basically hynix writes part no. except for ?hym? in by te 73~90 to use the limited 18 bytes from byte 73 to byte 90 6. not fixed but dependent 7. ck0~ck3 connected to dimm, tbd junction temp, cl2(3) support, intel defined concurrent auto precharge suport 8. refer to intel sp d specification 1.2b 9. in the case of l-part, character ?l? will be added between byte 81 and byte 82 10. refer to hynix web site byte 81~86 for l-part byte number function description function value note -p -s -p -s byte81 manufacturer?s part number(manufacturing site) b 42h 4, 5 byte82 manufacturer?s part number (power) l4ch4, 5 byte83 manufacturer?s part number (package type) t 54h 4, 5 byte84 manufacturer?s part number (component configuration) 8 (x8 based) 38h 4, 5 byte85 manufacturer?s part number (hyphent) - (hyphen) 2dh 4, 5 byte86 manufacturer?s part number (min. cycle time) p s 50h 53h 4, 5
pc100 sdram unbuffered dimm rev. 0.2/jul. 02 7 hym72v64756b(l)t8 series absolute maximum ratings note : operation at above absolute maximum rati ng can adversely affect device reliability. dc operating condition (t a =0 to 70 c ) note : 1.all voltages are referenced to v ss = 0v 2.v ih (max) is acceptable 5.6v ac pul se width with <=3ns of duration. 3.v il (min) is acceptable -2.0v ac pulse width with <=3ns of duration. ac operating test condition (t a =0 to 70 c , v dd =3.3 0.3v, v ss =0v) note : 1.output load to measure access times is equivalent to two ttl gates and one capacitor (50pf). for details, refer to ac/dc outp ut load circuit parameter symbol rating unit ambient temperature t a 0 ~ 70 c storage temperature t stg -55 ~ 125 c voltage on any pin relative to v ss v in , v out -1.0 ~ 4.6 v voltage on v dd relative to v ss v dd, v ddq -1.0 ~ 4.6 v short circuit output current i os 50 ma power dissipation p d 1w soldering temperature ? time t solder 260 ? 10 c ? sec parameter symbol min typ max unit note power supply voltage v dd , v ddq 3.0 3.3 3.6 v 1 input high voltage v ih 2.0 3.0 v ddq + 0.3 v 1,2 input low voltage v il -0.3 0 0.8 v 1,3 parameter symbol value unit note ac input high / low level voltage v ih / v il 2.4/0.4 v input timing measurement reference level voltage vtrip 1.4 v input rise / fall time tr / tf 1 ns output timing measurement reference level voltage voutref 1.4 v output load capacitance for access time measurement c l 50 pf 1
pc100 sdram unbuffered dimm rev. 0.2/jul. 02 8 hym72v64756b(l)t8 series capacitance (ta=25 c , f=1mhz) output load circuit parameter pin symbol -p/s unit min max input capacitance ck0~ck3 c i1 20 35 pf cke0,cke1 c i2 35 60 pf /s0~/s3 c i3 25 40 pf a0~12, ba0, ba1 c i4 40 100 pf /ras, /cas, /we c i5 40 100 pf dqm0~dqm7 ci 6 530pf data input / output capacitance dq0 ~ dq63 c i/o 525pf vtt=1.4v rt=250 ? 50pf output 50pf output dc output load circuit ac output load circuit
pc100 sdram unbuffered dimm rev. 0.2/jul. 02 9 hym72v64756b(l)t8 series dc characteristics i (ta=0 to 70 c , v dd =3.3 0.3v) note : 1.v in = 0 to 3.6v, all other pins are not tested under v in =0v 2.d out is disabled, v out =0 to 3.6 dc characteristics ii note : 1. i dd1 and i dd4 depend on output loading and cycle rates. specified values are measured with the output open 2. min. of trrc (refresh ras cycle time) is shown at ac characteristics ii 3. hym72v64756bt-p/s 4. hym72v64756blt-p/s parameter symbol min. max unit note input leakage current i li -18 18 ua 1 output leakage current i lo -2 2 ua 2 output high voltage v oh 2.4 - v i oh = -4ma output low voltage v ol -0.4vi ol = +4ma parameter symbol test condition speed unit note -p -s operating current i dd1 burst length=1, one bank active t rc t rc (min), i ol =0ma 1170 1170 ma 1 precharge standby current in power down mode i dd2p cke v il (max), t ck = min 36 ma i dd2ps cke v il (max), t ck = 36 precharge standby current in non power down mode i dd2n cke v ih (min), cs v ih (min), t ck = min input signals are changed one time during 2clks. all other pins v dd -0.2v or 0.2v 270 ma i dd2ns cke v ih (min), t ck = input signals are stable. 252 active standby current in power down mode i dd3p cke v il (max), t ck = min 56 ma i dd3ps cke v il (max), t ck = 56 active standby current in non power down mode i dd3n cke v ih (min), cs v ih (min), t ck = min input signals are changed one time during 2clks. all other pins v dd -0.2v or 0.2v 450 ma i dd3ns cke v ih (min), t ck = input signals are stable. 270 burst mode operating current i dd4 t ck t ck (min), i ol =0ma all banks active 1350 1170 ma 1 auto refresh current i dd5 t rrc t rrc (min), all banks active 3240 ma 2 self refresh current i dd6 cke 0.2v normal 56 ma 3 low power 28 ma 4
pc100 sdram unbuffered dimm rev. 0.2/jul. 02 10 hym72v64756b(l)t8 series ac characteristics i (ac operating conditions unless otherwise noted) note : 1.assume tr / tf (input rise and fall time ) is 1ns if tr & tf > 1ns, then [(tr+tf)/2-1]ns should be added to the parameter 2.access times to be measured with input si gnals of 1v/ns edge rate, from 0.8v to 2.0v if tr > 1ns, then (tr/2-0.5)ns should be added to the parameter parameter symbol -p -s unit note min max min max system clock cycle time cas latency = 3 tck3 10 1000 10 1000 ns cas latency = 2 tck2 10 12 ns clock high pulse width tchw 3 - 3 - ns 1 clock low pulse width tclw 3 - 3 - ns 1 access time from clock cas latency = 3 tac3 - 6 - 6 ns 2 cas latency = 2 tac2 - 6 - 6 ns data-out hold time toh 3 - 3 - ns data-input setup time tds 2 - 2 - ns 1 data-input hold time tdh 1 - 1 - ns 1 address setup time tas 2 - 2 - ns 1 address hold time tah 1 - 1 - ns 1 cke setup time tcks 2 - 2 - ns 1 cke hold time tckh 1 - 1 - ns 1 command setup time tcs 2 - 2 - ns 1 command hold time tch 1 - 1 - ns 1 clk to data output in low-z time tolz 1 - 1 - ns clk to data output in high-z time cas latency = 3 tohz3 3 6 3 6 ns cas latency = 2 tohz2 - 6 3 6 ns
pc100 sdram unbuffered dimm rev. 0.2/jul. 02 11 hym72v64756b(l)t8 series ac characteristics ii note : 1. a new command can be given trrc after self refresh exit parameter symbol -p -s unit note min max min max ras cycle time operation trc 70 - 70 - ns auto refresh trrc 70 - 70 - ns ras to cas delay trcd 20 - 20 - ns ras active time tras 50 100k 50 100k ns ras precharge time trp 20 - 20 - ns ras to ras bank active delay trrd 20 - 20 - ns cas to cas delay tccd 1 - 1 - clk write command to data-in delay twtl 0 - 0 - clk data-in to precharge command tdpl 2 - 2 - clk data-in to active command tdal 5 - 5 - clk dqm to data-out hi-z tdqz 2 - 2 - clk dqm to data-in mask tdqm 0 - 0 - clk mrs to new command tmrd 2 - 2 - clk precharge to data output hi-z cas latency = 3 tproz3 3 - 3 - clk cas latency = 2 tproz2 2 - 2 - clk power down exit time tpde 1 - 1 - clk self refresh exit time tsre 1 - 1 - clk 1 refresh time tref - 64 - 64 ms
pc100 sdram unbuffered dimm rev. 0.2/jul. 02 12 hym72v64756b(l)t8 series device operatin g option table hym72v64756b(l)t8-p hym72v64756b(l)t8-s cas latency trcd tras trc trp tac toh 100mhz(10ns) 2clks 2clks 5clks 7clks 2clks 6ns 3ns 83mhz(12ns) 2clks 2clks 5clks 7clks 2clks 6ns 3ns 66mhz(15ns) 2clks 2clks 4clks 6clks 2clks 6ns 3ns cas latency trcd tras trc trp tac toh 100mhz(10ns) 3clks 2clks 5clks 7clks 2clks 6ns 3ns 83mhz(12ns) 2clks 2clks 5clks 7clks 2clks 6ns 3ns 66mhz(15ns) 2clks 2clks 4clks 6clks 2clks 6ns 3ns
pc100 sdram unbuffered dimm rev. 0.2/jul. 02 13 hym72v64756b(l)t8 series command truth table note : 1. exiting self refresh occurs by asyn chronously bringing cke from low to high 2. x = don t care, h = logic high, l = logic low. ba =bank addr ess, ra = row address, ca = column address, opcode = operand code, nop = no operation command cken-1 cken cs ras cas we dqm addr a10/ ap ba note mode register set h x l l l l x op code no operation h x hxxx xx lhhh bank active h x l l h h x ra v read hxlhlhxca l v read with autoprecharge h write hxlhllxca l v write with autoprecharge h precharge all banks hxllhlxx hx precharge selected bank lv burst stop h x l h h l x x dqm h x v x auto refresh h h l l l h x x self refresh 1 entry h l l l l h x x exit l h hxxx x lhhh precharge power down entry h l hxxx x x lhhh exit l h hxxx x lhhh clock suspend entry h l hxxx x x lvvv exit l h x x
pc100 sdram unbuffered dimm rev. 0.2/jul. 02 14 hym72v64756b(l)t8 series package demension 29.21 15.80 29.21 29.21 15.80 29.21

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